Page 121 - Handout Digital Electronics

Step 3

Minimize the excitation table at all positions where the output (next states of flip flops A and B) are 1s
or xs. The functions to be minimized are for the equations JA, KA, JB and KB. For JA we minimize the
function using a three variable Karnaugh map. There is no need to minimize KA since J and K inputs are
combined.

X AB 00 01 10 11

0 X X X
X

1
1 1 X X X

JA = BX

KA = BX

X AB 00 01 11 10
0 X X X

1 X X 1
1 1 X X 1
JB = X

KB = X

The information from the excitation table after minimization is as follows:

JA = BX. JB = X.

KA = BX. KB = X .

From the logic equations the logic diagram should consist of an AND gate and two JK flip flops. The
inputs J and K determine the next state of the counter when a clock signal occurs. When both J and K =
0, the clock signal will have no effect.

The next step is to draw the circuit diagram from the logic equations.

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