Page 125 - Handout Digital Electronics

Figure 54: 4- bit asynchronous binary up counter

Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
. . . .
1 1 1 1

A time diagram explains better the operation of the above counter. To count from 0 to 15, sixteen (16)
clock pluses are needed. All the flip flops operate on the falling edge of the clock pulse. Since they are
connected in serial, the second flip flop (FF1) cannot change its state before the first flip flop (FF0)
changes its state. The same applies to the rest of the flip flops. This asynchronous up counter is also
called a ripple counter because for the last flip flop (FF3) to change its state the signal will have rippled
from the first flip flop (FF0) to FF3.

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