Page 129 - Handout Digital Electronics

LECTURE 17 SYNCHRONOUS BINARY COUNTERS
17.1 Introduction
These were developed to eliminate the major problems associated with asynchronous binary counters
namely:

• Slow speed of operation
• Erroneous counting at high frequencies when the number of bits involved is large.

In synchronous counters, the external clock signal is connected to the clock input of every individual flip
flop within the counter and in this way all flip flops are clocked together simultaneously at the same
time. This gives a fixed time relationship. This means changes at the output occur in synchronization
with the clock signal. The individual output bits change state at the same time in response to a common
clock pulse. So, in synchronous counters there are no ripple effects and so no propagation delays.

17.2 A 4-bit binary synchronous up counter

Figure 58: A 4-bit binary synchronous up counter

Operation

The J and K inputs of the first flip flop(FF0) are tied to a high(5v), so this flip flop is ready to toggle
whenever a clock pulse(C = 1) is applied. Initially all the flip flops are set to zero (0), that is Q0 = 0, Q1
= 0, Q2 = 0 and Q3 = 0. When a clock pulse is applied to FF0, the present state Q0 = is complemented to
1. The 1 displaces the zero which propagates to the J and K inputs of FF1 and to the inputs of the first
AND gate. With J = K = 0, C =1, FF1 does not change its state. The same applies to FF2 and FF3. In the
next count, Q0 =1 is complemented to a zero. The zero displaces the 1 which propagates to the J and K
inputs of FF1. So, the inputs to FF1 are J = K =1, C =1. The present state of FF1 (Q1 = 0) is
complemented to a 1. The 1 displaces zero which propagates to the J and K inputs of FF2 as well as to
the inputs of the second AND gates. So, the situation is Q0 = 0, Q1 = 1, Q2 and Q3 = 0.

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