Page 131 - Handout Digital Electronics

The table below summarizes the operation of this synchronous counter.

Q3 Q2 Q1 Q0 J K C
0 0 0 1 1 1 1
0 0 1 0 1 1 1
0 0 1 1 1 1 1
0 1 0 0 1 1 1
. . . . 1 1 1
. . . . 1 1 1
1 1 1 . 1 1 1

The time diagram is the same as that of an asynchronous up counter; the only difference is that the
propagation delays are not there.

17.3 A 4-bit binary synchronous down counter

Figure 59: 4-bit synchronous binary down counter

The basic operation of a synchronous down counter is the same as that of a synchronous up counter. The
only difference is that initially all the flip flops are set at a predefined value, in this case 15.

Operation

Initially all the flip flops are set to 1, that is Q0 = 1, Q1 = 1, Q2 = 1 and Q3 = 1. The J and K inputs of
FF0 are tied to a high, so it is ready to toggle whenever a clock pulse (C =1) is applied to it. When a
clock pulse is applied, the present state of FF0 (Q = 1) is complemented to a zero (0). When Q was a 1,

not Q ( Q ) was a zero. When Q changed to 0, Q changed to a 1, so the one at Q output displaces the
zero which propagates to the J and K inputs of FF1 and the inputs of the first AND gate. The situation is:
J = 0, K = 0 and C= 1. FF1 does not change its state. The same applies to FF2 and FF3. The rest of the
counting down follows the above pattern. Note that the in the synchronous down counter, the J and K
inputs as well as the AND gates control the flip flops from changing their states simultaneously. Like in
the synchronous counter, the time diagram of the asynchronous down counter and that of the
synchronous counter are the same except that in the synchronous up counter the propagation delays are
not noticeable.

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