Page 134 - Handout Digital Electronics

Figure 62: parallel load register implemented on D flip flops

The above parallel load register operates as follows:

All the bits of the register are loaded simultaneously with a common clock pulse
transition, for example a clock transition applied to the clock, will load all the four inputs d0 – d3.
Assume a binary word 1101 is to be loaded into the register (The leftmost bit is the MSB, and the
rightmost bit is the LSB).A3 will 1, A2 will be 1, A1 will be 0 and A0 will be 1. (See figure 62). If the
contents of the register must be left unchanged then the clock should be inhibited from the circuit that is
the clock must be zero. To reset the register the CLEAR (CLR) signal is used (uses negative logic).

Figure 62: parallel load register with simulated signals

Computer data registers can also be implemented on SR flip flops as shown below in figure 63.

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