Page 135 - Handout Digital Electronics

Figure 63: Parallel load register implemented on SR flip flops

In the SR parallel load register above, do d1, d2 and d3 are input data lines and d4, d5, d6 and d7 are out
lines. The R input is tied to a reset line to avoid the ambiguous case arising. The input data strobe line
must always be a high to accept data in the register. The same applies to the output data strobe. To
parallel load the bit stream 1101, the input data strobe is set to a high, data and the bits are applied to the
respective input lines. With a high output data strobe, the bits will simultaneously appear at the
respective output lines d4-d7. Figure 64 shows the simulated signals

Figure 64: SR parallel load register showing simulated signals

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