Page 140 - Handout Digital Electronics
P. 140
18.6 Parallel in Serial out (PISO) register
Figure 70: Parallel in serial out shift register
In the PISO shift register above, d0 – d3 are the parallel inputs. The Clear pulse is low level (binary
zero). It is initially applied to reset all the flip flops to zero (0). Assume a four-bit word 1101 is to be
parallel loaded and serially output. The write enable control signal is activated with a binary 1. FF0 will
be 0, FF1 will be 1, FF3 will be 0 and FF3 will be 0. The Preset control signal is active low, so the four-
bit data word 1101 will be stored in the shift register. To read out the stored four-bit word in serial
forward four clock pulses are applied to shift the stored bits to the right.
Figure 71: Parallel in serial out with simulated signals.
140
