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18.6 Parallel in Parallel out (PIPO) register
In the PIPO shift register above, d0 – d3 are the parallel input and Q0 – Q2 are the parallel outputs. All
the data bits at d0-d3 appear on the parallel outputs immediately following the simultaneous entry of the
data bits. The above circuit is a four- bit parallel out shift register constructed on D flip flops. When a
clock pulse is applied, all the data bits at the D (d0-d3) inputs appear at the corresponding Q outputs
simultaneously. The clear is a low-level signal used to reset the contents of the shift register. The PIPO
is a universal register that can be used to output data serially. The set can be used to select one of the
modes of shifting.
Figure 72: Parallel in parallel out shift register.
Figure: 73 PIPO shift register with simulated signals
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