Page 33 - UNI 101 Computer Science Handout.

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memory and one or more I/O devices. An I/O module receives commands from the CPU and provides

the control of the I/O device or devices so as to execute those commands. It also responds to requests

from devices and provides interrupt service to the CPU to process those requests. 5. The buses
connecting the various components together. The buses may be an integral part of the architecture of

the system or may simply be a point-to-point connection between other components, depending on the

architectural design. The pathways include a required connection between the CPU and the I/O module
to enable the CPU to issue programmed I/O commands to the I/O module and also for the I/O module

to provide service request, special condition, and completion interrupt signals to the CPU. The

connection from the I/O module to the device or devices is required both for I/O module control of the

devices and as a passageway for the data. There must be a connection between the I/O module and

memory for DMA to take place. Although the illustration implies that these pathways represent actual
direct connections between the various component blocks, this is not actually true. The connections

could be direct or they could be electronic switches that provide the connections at the time they are

required.

For example, memory and the I/O modules could each be attached to different buses that are
connected together when DMA takes place, or the I/O module could be attached by separate

connections both to memory and to the CPU. These differences constitute different computer system

architectures, representing different vendors, different goals, and different design philosophies. In
nearly every system, one or more buses form the backbone for connection of the various components,

memory and I/O, to the CPU. In simplest form, a single system bus could connect the CPU to memory

and to all the various modules that control I/O devices. Of course this approach would subject the overall

performance of the system to the limited bandwidth of a single bus. More commonly, the system bus in

a bus architecture connects through one or more bus interface circuits to a number of different
interconnected buses.

33 Academic Year 2025/2026