Page 197 - Programmable Logic Controllers, Fifth Edition - Mobile version

Timer Ladder logic program
Input input T4:0 Output
TON
L1 TIMER ON DELAY EN L2
DN Timer T4:0 DN
S1 Time base 1.0
Timer Preset 10000 Light
input Accumulated 0

T4:0
CTU
COUNT-UP COUNTER CU
DN Counter C5:0 DN
Preset 100
Accumulated 0
Timer
input C5:0
RES

C5:0 Light

DN

Figure 8-37 Timer driving a counter to produce an extremely long time-delay period.

HSC counter. Only one HSC instruction can be used in a
High-speed counter CU program.
Type Up
Counter C5:0 CD • The high-speed counter instruction address is fixed
Preset 0 at C5:0.
Accum 0 DN
• This counter instruction can be programmed as
Figure 8-38 Program for Problem 1. either an up-counter or bidirectional (Up/Down)
counter.
HSC instruction may be imbedded in the CPU, or fixed • The hardware counter’s accumulator increments
hardware, or a separate module. or decrements in response to external input
Figure 8-38 shows a high-speed up-counter instruction signals.
for an Allen-Bradley MicroLogix controller. This particu- • The input filter response time is the time from the
lar controller has an imbedded high-speed counter that is external input voltage reaching an on or off state
able to perform counts of events between the scan of the to the micro controller recognizing that change of
program. Then, when the program actually scans through state. The higher you set the response time, the lon-
it can see the count value that the counter has reached. ger it takes for the input state change to reach the
• The controller has one 20 KHz high-speed coun- micro controller. However, setting higher response
ter, which means it would be able to count 20,000 times also provides better filtering of high frequency
pulses per second. noise.
• The high-speed counter operates independently of • When the high-speed counter is enabled, data table
the controller scan. counter C5:0 is used by the ladder program for
• The HSC instruction is used to configure, control, monitoring the high-speed counter accumulator and
and monitor the controller’s internal hardware status.

178 Chapter 8 Programming Counters

pet73842_ch08_156-183.indd 178 03/11/15 3:58 PM