Page 92 - Programmable Logic Controllers, Fifth Edition - Mobile version
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A                                               A
                         B                                               B
                         C                                    Y
                         D                                               C
                                                                                                                          Y
                                           (a)                           D

                                                                         E
                    A                                                    F

                    B
                                                                                                 (f )
                    C                                              Y
                                                                         Figure 4-31  (Continued )

                                                                          3.  The logic circuit of Figure 4-32 is used to activate an
                    D
                                                                              alarm when its output Y is logic HIGH or 1. Draw a
                                           (b)
                                                                              truth table for the circuit showing the resulting out-
                                                                              put for all 16 of the possible input conditions.
                                                                          4.  What will be the data stored in the destination
                         A                                                    address of Figure 4-33 for each of the following
                                                                              logical operations?
                         B                                                    a. AND operation
                                                              Y               b. OR operation
                         C                                                    c. XOR operation
                                           (c)                            5.  Write the Boolean expression and draw the gate
                                                                              logic diagram and typical PLC ladder logic dia-
                                                                              gram for a control system wherein a fan is to run
                                                                              only when all of the following conditions are met:
                    A                                                         •  Input A is OFF

                    B                                                         •  Input B is ON or input C is ON, or both B and C
                                                                                are ON
                                                                              •  Inputs D and E are both ON
                    C                                                         •  One or more of inputs F, G, or H are ON


                                                                             A
                    D                                              Y
                                                                             B                                     Alarm
                                                                                                               Y
                    E                                                       C

                                         (d)                                D
                                                                         Figure 4-32  Logic circuit for Problem 3.


                          A                                                   Source A  0 00 0000 01 0     1 01 01    0

                          B
                                                             Y                 Source B 0 00 00000 111  01 01         1
                          C
                          D
                                                                             Destination
                                           (e)
                   Figure 4-31  Logic gate circuits for Problem 2.       Figure 4-33  Data for Problem 4.



                                                                                     Fundamentals of Logic  Chapter 4    73







          pet73842_ch04_061-073.indd   73                                                                               03/11/15   3:52 PM
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