Page 1145 - Basic Electrical Engineering

• 484: 16-bit random access memory

• 485: 4-bit magnitude comparator

• 486: Quad 2-input XOR gate

• 487: 4-bit true/complement/zero/one element

• 488: 256-bit read-only memory
• 489: 64-bit random access memory

• 490: Decade counter (separate divide-by-2 and divide-by-5 sections)

• 491: 8-bit shift register, serial in, serial out, gated input

• 492: Divide-by-12 counter (separate divide-by-2 and divide-by-6 sections)

• 493: 4-bit binary counter (separate divide-by-2 and divide-by-8 sections)

• 494: 4-bit shift register, dual asynchronous presets
• 495: 4-bit shift register, parallel In, parallel out, serial input, bidirectional

• 496: 5-bit parallel-in/parallel-out shift register, asynchronous preset

• 497: Synchronous 6-bit binary rate multiplier

• 498: 4-bit data selector/storage register

• 499: 4-bit bidirectional universal shift register
• 4100: Dual 4-bit bistable latch

• 4101: AND-OR-gated J-K negative-edge-triggered flip-flop with preset

• 4102: AND-gated J-K negative-edge-triggered flip-flop with preset and clear

• 4103: Dual J-K negative-edge-triggered flip-flop with clear

• 4104: J-K master–slave flip-flop
• 4105: J-K master–slave flip-flop

• 4106: Dual J-K negative-edge-triggered flip-flop with preset and clear

• 4107: Dual J-K flip-flop with clear

• 4107A: Dual J-K negative-edge-triggered flip-flop with clear

• 4108: Dual J-K negative-edge-triggered flip-flop with preset, common clear, and common clock
• 4109: Dual J-Not-K positive-edge-triggered flip-flop with clear and preset

• 4110: AND-gated J-K master-slave flip-flop with data lockout

• 4111: Dual J-K master-slave flip-flop with data lockout