Page 16 - Z370 AORUS Gaming 7 Rev 1.0 Introduction -171024

CFL S Flow Diagram for SYS_PWROK / PCH_PWROK Generation

＊PROCPWRGD : Indicates that VCCST, VCCSTG, VCCPLL, VCCPLL_OC, VCCIO, VCCSA, VDDQ SVID Transaction
(and for OPC SKUs, VCCOPC_1p8) power supplies and clocks are stable. This signal will be asserted
only after PCH_PWROK assertion.
＊VCCST_PWRGD : Indication that the VCCST\VDDQ power supplies are stable and within
specification . CPU SVID SVID
SLP_S3#
S4 PWM
VRs VR_ON CFL S
EN PGD VR_READY
VCCST_PWRGD

VCCST SIO Level
PwrGate Delay(ms) Shifter

EN PGD N_PCH_VRMPWRGD
SYS_PWROK

VCCIO V3.3S PROCPWRGD
VR
EN PGD

PLTRST#
Other
S0 VRs PWOK SIO PWROK1
EN PGD Delay
(ms) PCH_PWROK
ATX PSU Negative
VM PWOK PCH
Edge
EN PGD Detect

SLP_S3#

SLP_S4#

P.16 Dept : #41B 研發服務部 By : Engineering