Page 379 - FUNDAMENTALS OF COMPUTER

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NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 379

and executes them. For every computer there is H$aVm h¡& àË`oH$ H$åß`yQ>a _| Hw$N> B§ñQ´>ŠeÝg Ho$ goQ> hmoVo
a set of instructions that can be executed by the h¢, {OÝh| àmogoga Ûmam EŠOrŠ`yQ> {H$`m OmVm h¡& BZ goQ²>g
processor. This set is called as Instruction set of H$mo H$åß`yQ>a H$m B§ñQ´>ŠeZ goQ> H$hm OmVm h¡&
the computer.
Instruction set of computer may contain H$åß`yQ>a Ho$ B§ñQ´>ŠeZ goQ> H$mo B§ñQ´>ŠeÝg H$s
following categories of instructions: {ZåZmZwgma lo{U`m| _| ~m§Q>m Om gH$Vm h¡:

1. Arithmetic Instructions 1. A[aW_o{Q>H$ B§ñQ´>ŠeÝg
2. Logical Instructions 2. cm°{OH$c B§ñQ´>ŠeÝg
3. Shift & Rotate instruction 3. {eâQ> E§S> amoQ>oQ> B§ñQ´>ŠeÝg
4. Data Transfer Instructions 4. S>mQ>m Q´>m§g\$a B§ñQ´>ŠeÝg
5. Machine control Instructions 5. _erZ H§$Q´>moc B§ñQ´>ŠeÝg
6. Input-output Instructions 6. BZnwQ>-AmCQ>nwQ> B§ñQ´>ŠeÝg
7. Branching instructions 7. ~«m§qMJ B§ñQ´>ŠeÝg

5.2 Addressing Modes 5.2 ES´>oqgJ _moS>²g
Addressing Modes may be defined as dif- {H$gr {ZX}e _| Am°na|S> H$mo Xem©Zo Ho$ {^ÝZ VarH|§$ hr
ferent ways to specify operands in an instruc- ES´>oqgJ _moS>²g H$hcmVo h¢Ÿ& AV… à˶oH$ B§ñQ´>³eZ BgHo$
tion. Therefore each instruction may use its
own addressing mode. The number of address- ñd¶§ Ho$ ES´>oqgJ ‘moS> H$m Cn¶moJ H$a gH$Vm h¡& BZH$s
ing modes depend upon the type of processor. g§»`m àmogoga Ho$ àH$ma na {Z^©a H$aVr h¡Ÿ& {ZåZ àH$ma
Following addressing modes are common in Ho$ ES´>oqgJ _moS>²g gm_mÝ`V: nmE OmVo h¢…
processors:
1. Implied mode. 1. BåßcmB©S> _moS>
2. Immediate mode. 2. B_r{OEQ> _moS>
3. Register Mode. 3. a{OñQ>a _moS>
4. Register Indirect Mode. 4. a{OñQ>a BÝS>m`aoŠQ> _moS>
5. Autoincrement or Autodecrement mode. 5. Am°Q>moBÝH«$s_|Q> `m Am°Q>mo{S>{H«$_|Q> _moS>
6. Direct Address Mode. 6. S>m`aoŠQ> ES´og _moS>
7. Indirect Address Mode. 7. BÝS>m`aoŠQ> ES´>og _moS>
8. Relative Address Mode. 8. [aco{Q>d ES´>og _moS>
9. Indexed Addressing mode. 9. B§S>oŠñS> ES´>oqgJ _moS>
10. Base Register Addressing. 10. ~og a{OñQ>a ES´>oqgJ _moS>

5.2.1 Implied Addressing Mode 5.2.1 BåßcmB©S> ES´>oqgJ _moS>
In this addressing mode operand is hid- Bg àH$ma Ho$ ES´>oqgJ _moS> _| Am°na|S> Am°nH$moS> _| hr
den in opcode part. For example, consider fol- Nw>nm hmoVm h¡& O¡go, {ZåZ{b{IV 8085 BÝñQ´>³eZ na
lowing 8085 instruction: {dMma H$a|…
CMA