Page 383 - FUNDAMENTALS OF COMPUTER

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NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 383

Direct address is used in IN and OUT in- IN VWm OUT {ZX}emo§ _|§ nmoQ>© ES´>og grYo Cn`moJ
struction _| AmVm h¡Ÿ&
Instruction Memory / Port
memory / Port Address datum

5.2.7 Indirect Addressing Mode 5.2.7 BÝS>m`aoŠQ> ES´>oqgJ _moS>
The address specified in the instruction is {ZX}e _| Omo ES´>og hmoVm h¡, Cgo BÝS>m`aoŠQ> ES´>og
the indirect address. This address holds the H$hVo h¢ Š`m|{H$ Bg ES´>og na S>mQ>m H$m ES´>og hmoVm h¡Ÿ&
address of the operand.

Instruction Memory Memory

Indirect E A datum

Address
e.g. 8086 INT n instruction. Here n points O¡go, 8086 Ho$ INT n {ZX}eŸ& `hm§ na n go Mma
to four physical addresses starting from 4n. CS ^m¡{VH$ ES´>og àmaå^ hmoVo h¢ & BZ ES´>ogog na CS d IP
and IP are loaded from these addresses. Now Ho$ ZE Zå~a hmoVo h¢Ÿ& CS VWm IP H$s _XX go AJco {ZX}e
values of CS & IP generate next Instruction
address. H$m ES´>og àmßV {H$`m OmVm h¡Ÿ&

5.2.8 Relative Addressing Mode 5.2.8 [aco{Q>d ES´>oqgJ _moS>
In this mode, effective address of the in- Bg ‘moS> ‘|, BÝñQ´>³eZ H$m B’o$p³Q>d ES´>og BÝñQ´>³eZ
struction is calculated from the contents of ‘| {ZYm©[aV {S>ñßbog‘oÝQ> H$mo Omo‹S>H$a àmoJ«m‘ H$mCÊQ>a
program counter (Instruction Pointer) by add-
ing the displacement specified in the instruc- (BÝñQ´>³eZ nm°BÝQ>a) Ho$ H$ÝQ>oÝQ> go JUZm {H$¶m OmVm h¡&
tion. Consider following 8086 instruction:
JMP 46H
JMP 2A62H
JC 39H
CALL 401FH
LOOP F2H
Block diagram representation of this type Bg àH$ma Ho$ {ZX}e H$mo ãcm°H$ S>m`J«m_ Ho$ ê$n _|
of instruction is as follows: {ZåZmZwgma Xem© gH$Vo h¢…
Instruction
Displacement

⊕
IP

Effective Address