Page 387 - FUNDAMENTALS OF COMPUTER

NPP

NPP CPU Architecture, Addressing Modes and Data Transfer Schemes 387

Instruction Microoperation
MOV A, R 1 M[A] ← R 1
ADD R , C R ← R + M[C]
2 2 2
R 1
DIV R , X R ← MX
[]
1
1
The instruction MOV A, B is not allowed {ZX}e MOV A, B Zht McoJm Š`m|{H$ Bg_| XmoZm|
because both source and destination cannot be Am°na|S> _o_moar h¡Ÿ&
memory.

3. One-Address Instruction 3. EH$-ES´>og {ZX}e
In this instruction only one operand is Bg àH$ma Ho$ {ZX}e _| {g\©$ EH$ hr Am°na|S> ~VmVo h¢Ÿ&
specified in the operand. It has following for- BgH$m \$m°_}Q> Bg àH$ma hmoVm h¡:
mat:

Instruction
Opcode Operand

Second operand is implied and it resides Xygam Am°na|S> ñdV: EŠ`yå`ycoQ>a (AC) _mZ {c`m
in Accumulator (AC). For example, consider OmVm h¡Ÿ& CXmhaUV:, {ZåZ {ZX}e XoImo:
following instruction:
ADD A

This will perform following operation: `h {ZX}e {ZåZ {H«$`m H$aoJm:
AC ← M [A] + AC
That means the contents of memory word AWm©V ‘o‘moar dS>© Ho$ H$ÝQ>oÝQ²>g {OZH$m ES´>og A h¡
whose address is A will be added to contents (AC) Ho$ H§$Q>|Q> Cg _o_moar Ho$ H§$Q>|Q> go Ow‹S>|Jo VWm n[aUm_
of AC and the result would be placed in AC.
AC _| OmEJmŸ&
When data is to be transferred from O~ _o_moar go S>mQ>m H$mo AC _| ^oOZm hmo V~ cmoS>
memory to AC, load instruction is used e.g. : Zm_H$ {ZX}e H$m Cn`moJ hmoVm h¡Ÿ& O¡go:

LOAD A
This will perform following micro-opera- `h {ZX}e {ZåZ {H«$`m H$aoJm:
tion:
AC M[A]
Similarly, AC to memory transfer can be Bgr àH$ma, AC go _o_moar hoVw ñQ>moa BÝñQ´>³eZ H$m
specified with store instruction e.g. : Cn`moJ hmoJmŸ& O¡go:
STORE B
M[B] AC
Following example instructions and the {ZåZ Q>o~c _| EH$ Am°na|S> {ZX}e d g§~§{YV
corresponding microoperation: _mBH«$moAm°naoeZ Ho$ CXmhaU {XE JE h¢: