Page 391 - FUNDAMENTALS OF COMPUTER
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                  NPP         CPU Architecture, Addressing Modes and Data Transfer Schemes         391


                     r can be any 8-bit register or 16-bit general  ·  r H$moB© ^r 8-{~Q> a{OñQ>a `m 16 {~Q> a{OñQ>a hmo
                      register. It can be segment register.       gH$Vm h¡& `h goJ_|Q> a{OñQ>a hmo gH$Vm h¡&

                     This instruction is exactly similar to MOV  · `h B§ñQ´>ŠeZ MOV r, m Ho$ g_mZwê$n h¡& Ho$dc
                      r, m. Only source and destination has been  gmog© Ed§ S>opñQ>ZoeZ EŠgM|O hmo JE h¢&
                      exchanged.
                     If a 16-bit register is specified Lower byte  · `{X 16-{~Q> a{OñQ>a {ZYm©[aV h¡ Vmo cmoAa ~mBQ>
                      is transferred to m and Higher byte to m+1.  m H$mo Q´>m§g\$a H$a| Ed§ hm`a ~mBQ> m+1 H$mo AWm©V²
                      e.g.
                                                       MOV   [BX] ,  AX
                      This instruction will  be executed  as  fol-  B§ñQ´>ŠeZ H$mo {ZåZmZwgma EŠOrŠ`yQ> {H$`m OmEJm:
                  lows:
                                      (AL)                             [BX]        ; Low Byte transfer

                                      (AH)                             [BX + 1]  ; High Byte transfer
                      MOV m, data: Specified data is transferred  MOV m, data: B§ñQ´>ŠeZ _| ñno{g\$mBS> B\o${ŠQ>d
                  into the data segment at the effective address  ES´>og _| S>mQ>m goJ_|Q> Ho$ A§Xa ñno{g\$mBS> S>mQ>m Q´>m§g\$a
                  specified in the instruction.               {H$`m J`m h¡&
                     If data is 8-bit wide, only one location is  · `{X S>mQ>m 8-{~Q> dmBS> h¡, Ho$dc EH$ cmoHo$eZ H$m
                      used: e.g.                                  Cn`moJ {H$`m J`m h¡ AWm©V²

                                                       MOV   [BX], 42H
                      8-bit datum 42H is to be transferred into   BX Ûmam nm°B§Q>oS> B\o${ŠQ>d ES´>og _| S>mQ>m goJ_|Q> _|
                  the physical memory location in data segment  {\${OH$c _o_moar cmoHo$eZ Ho$ A§Xa 8-{~Q> S>oQ>_ 42H
                  at effective  address pointed  by  BX. Thus  the  Q´>m§g\$a {H$`m h¡& AV:  {\${OH$c  ES´>og  (BX) VWm
                  physical address  will be  sum of (BX) and
                  (DS) × 16.                                  (DS) ×16 H$m g_ hmoJm&
                     If a 16-bit datum is specified two memory  · `{X 16-{~Q> S>oQ>_ ñno{g\$mBS> h¡ Vmo Xmo _o_moar
                      locations will be used. Low byte will go    cmoHo$eÝg H$m Cn`moJ hmoJm& cmo ~mBQ> ñno{g\$mBS>
                      into the  memory location  specified and    _o_moar cmoHo$eZ _| VWm hmB ~mBQ> ZoŠñQ> _o_moar cmoHo$eZ
                      high  byte  will go into the  next memory
                      location.  e.g.                             _| OmEJm& CXmhaU:
                                                      MOV  [SI],  36A2H
                      A2H is transferred to [SI] in DS            A2H DS _| [SI]  _| Q´>m§g\$a H$a|&

                      36H is transferred to [SI + 1] in DS        36H DS _| [SI + 1]  _| Q´>m§g\$a H$a|&
                     Displacement can also be specified.     · {S>gßcog_|Q> H$mo ñno{g\$m` H$a|&
                      XCHG r , r : The  contents of  registers    XCHG r , r : a{OñQ>a r VWm r Ho$ H§$Q>|Q²>g EŠgM|O
                                                                                    1
                                                                           2
                                                                         1
                                                                                         2
                                2
                              1
                  r  and r  are exchanged.                    hmo JE h¢&
                         2
                   1
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