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6.7 Variable- Length Instructions .......................................................................................................... 149
6.8 Example Microprocessor Register Organizations ........................................................................... 165
6.9 INSTRUCTION CYCLE ....................................................................................................................... 166
6.10 REDUCED INSTRUCTION SET ARCHITECTURE ............................................................................... 168
6.10.1Characteristics of Reduced Instruction Set Architectures ...................................................... 170
6.11 CISC versus RISC Characteristics ................................................................................................... 172
6.12 RISC PIPELINING ............................................................................................................................ 174
6.12 1 Optimization of Pipelining ...................................................................................................... 176
6. 13 RISC VERSUS CISC CONTROVERSY ................................................................................................ 178
Chapter seven ........................................................................................................................................... 180
7.1 Introduction .................................................................................................................................... 181
7.2 MICRO- OPERATIONS ...................................................................................................................... 181
7.2.1 The Fetch Cycle ........................................................................................................................ 182
7.2.2 The Indirect Cycle ..................................................................................................................... 184
7.2.3 The Instruction Cycle ................................................................................................................ 186
7.3 CONTROL OF THE PROCESSOR ........................................................................................................ 187
7.3.1 Functional Requirements ......................................................................................................... 187
7.4 Internal Processor Organization ..................................................................................................... 191
7.5 HARDWIRED IMPLEMENTATION..................................................................................................... 196
7.6 VECTOR COMPUTATION ................................................................................................................. 198
7.8 Approaches to Vector Computation ............................................................................................... 199
7.9 What is Vector Computation? ........................................................................................................ 204
7.10 The SIMD Architecture .............................................................................................................. 204
7.11 Key Technical Components ........................................................................................................... 204
7.11.1 Vector Registers ..................................................................................................................... 204
7.11.2. Vector Functional Units (Pipelines) ....................................................................................... 204
7.11.3. Vector Length and Stride ...................................................................................................... 205
7.12 Why does it matter today? ........................................................................................................... 205
7.12.1 Deep Dive: Vectorization ....................................................................................................... 205
Reference .................................................................................................................................................. 206
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