Page 168 - Programmable Logic Controllers, Fifth Edition

L1 Input Ladder logic program Output L2 Figure 7-34 Cascading of timers for
longer time delays.
SW TON
TIMER ON DELAY EN
Timer T4:1 PL
SW Time base 1.0
Preset 30000 DN
Accumulated 0
T4:1
TON
TIMER ON DELAY EN
DN Timer T4:2
Time base 1.0 DN
Preset 12000
Accumulated 0

T4:2 PL

DN

Ladder logic program • The input to timer T4:0 is controlled by the T4:2
done bit.
Red time
T4:2 TON • The input to timer T4:1 is controlled by the T4:0
TIMER ON DELAY EN Outputs L2
Timer T4:0 done bit.
DN Time base 1.0 • The input rung to timer T4:2 is controlled by the
Preset 30 DN Tra c lights
Accumulated 0 T4:1 done bit.
Red Red
Green time • The timed sequence of the lights is:
T4:0 TON Red—30 s on
TIMER ON DELAY EN
Timer T4:1 Green—25 s on
DN Time base 1.0 Amber Amber Amber—5 s on
Preset 25 DN
Accumulated 0 • The sequence then repeats itself.

Amber time Green Green The chart shown in Figure 7-36 shows the timed se-
T4:1 TON quence of the lights for two-directional control of traffic
TIMER ON DELAY EN
Timer T4:2 lights.
DN Time base 1.0 Figure 7-37 shows the original traffic light program
Preset 5 DN modified to include three more lights that control traffic
Accumulated 0
flow in two directions.
T4:0 T4:0 Red

EN DN
T4:1 T4:1 Green

EN DN
T4:2 T4:2 Amber

EN DN
Figure 7-35 Control of traffic lights in one direction.

Red = north/south Green = north/south Amber = north/south

Green = east/west Amber = east/west Red = east/west
25 s 5 s 25 s 5 s
Figure 7-36 Timing chart for two-directional control of traffic lights.

Programming Timers Chapter 7 149

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