Page 172 - Programmable Logic Controllers, Fifth Edition

L1 Input LS1 TOF Ladder logic program Outputs L2
TIMER OFF DELAY
1 Timer T4:0 EN
LS1 Time base 1 SOL A
Preset 25 DN
Accumulated 0

SOL B
T4:0 SOL A
2 R R
DN
T4:0 SOL B
Y Y
3
DN

T4:0 R
4
EN
T4:0 Y
5
EN
Figure 7-41 Ladder logic program for Problem 4.

d. When is the timer reset? h. Assume that your accumulated time value is up
e. When will rung 3 be true? to 020 and power to your system is lost. What
f. When will rung 5 be true? will your accumulated time value be when
g. When will output PL4 be energized? power is restored?

Inputs Ladder logic program Outputs
Figure 7-42 Ladder
L1 PB1 T4:5 L2 logic program for
1 RES Problem 5.
PB1
PL1
PB2
RTO PL2
PB2
RETENTIVE TIMER ON
2 Timer T4:5 EN
Time base 1.0 PL3
Preset 50 DN
Accumulated 0
PL4
T4:5/EN PL1
3

T4:5/EN PL2
4
T4:5 DN PL3
5

T4:5 DN PL4
6

Programming Timers Chapter 7 153

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