Page 171 - Programmable Logic Controllers, Fifth Edition

L1 Stop Start L2 j. Suppose that rung 1 is true for 5 s and then
PB2
PB1 OL power is lost. What will the accumulated value
M of the counter be when power is restored?
4. Study the ladder logic program in Figure 7-41 and
Hand M-1
answer the questions that follow:
Auto TD a. What type of timer has been programmed?
PS1 b. What is the length of the time-delay period?
c. What is the value of the accumulated time when
TD-1 TD-2 power is first applied?
d. When does the timer start timing?
e. When does the timer stop timing and reset itself?
(60 s)
f. When input LS1 is first closed, which rungs are
Figure 7-39 Hardwired relay control circuit for Problem 2. true and which are false?
g. When input LS1 is first closed, state the status
(on or off) of each output.
c. What is the value of the accumulated time when h. When the timer’s accumulated value equals the pre-
power is first applied? set value, which rungs are true and which are false?
d. When does the timer start timing? i. When the timer’s accumulated value equals the
e. When does the timer stop timing and reset itself? preset value, state the status (on or off) of each
f. When input LS1 is first closed, which rungs are output.
true and which are false? j. Suppose that rung 1 is true for 5 s and then
g. When input LS1 is first closed, state the status power is lost. What will the accumulated value
(on or off) of each output. of the counter be when power is restored?
h. When the timer’s accumulated value equals the pre- 5. Study the ladder logic program in Figure 7-42, and
set value, which rungs are true and which are false? answer the questions that follow:
i. When the timer’s accumulated value equals the a. What type of timer has been programmed?
preset value, state the status (on or off) of each b. What is the length of the time-delay period?
output. c. When does the timer start timing?

Input Ladder logic program Outputs
LS1 TON
L1 L2
1 TIMER ON DELAY EN
LS1 Timer T4:0
Time base 1 SOL A
Preset 10 DN
Accumulated 0
SOL B
T4:0 SOL A
2
R R
DN
T4:0 SOL B
3 Y Y
DN
T4:0 R
4
EN
T4:0 Y
5
EN
Figure 7-40 Ladder logic program for Problem 3.

152 Chapter 7 Programming Timers

pet73842_ch07_131-155.indd 152 05/11/15 4:22 PM