Page 1099 - Basic Electrical Engineering
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Figure 16.20 Clocked RS flip-flop
When the clock input is high (i.e., 1) the flop-flip will be set for R = 0 and
S = 1 and will be reset for R = 1 and S = 0 as has been shown in the truth
table.
Truth table for a clocked RS flip-flop
Figure 16.21 Clocked SR flip-flop
