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KBL S Flow Diagram for RSMRST#/DSW_PWROK Generation
Other Pwrgood
Signals feeding into
ALL_SYS_PWRGD
Other S5 +VccPrim_1p0
VRs +VccPrim_1p8
EN PGD +VccPrim_3p3 PCH
VCCPRIM_1P0
VCC1_0_PCH ALL_SYS_PWRGD
VCCPRIM
1.0V
VR
EN PGD
VCCPRIM_1P8
SUSWARN#/
VCCPRIM SUSPWRDNACK
1.8V To Board Logic/EC
VR
EN PGD
SUSACK#
VCC3_PCH VCCPRIM_3P3
VCCPRIM
3.3V RSMRST#
VR Delay 10ms RSMRST#
EN PGD
+5VSB
3VDUAL_PCH
DSW Voltage
3.3V Monitor N_PCH_DPWROK
VR DSW_PWROK
Brd EN PGD Delay 10ms
Logic
N_-DEPSLP SLP_SUS#
Dept : #41B研發服務部 By: P.4
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