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KBL Timing Diagram for G3 to S0/M0 [Non-Deep Sx Platform]/1

VccRTC
tPCH01 : VccRTC stable to RTCRST# high and SRTCRST# high
RTCRST#
tPCH04 : VccRTC stable to start of VccDSW voltage ramp 3VDUAL_PCH
VccDSW3_3
tPCH05 : RTCRST# high to DSW_PWROK high N_PCH_DPWROK
DSW_PWROK tPCH02 : VccDSW stable to DSW_PWROK high

SLP_SUS# Note 1 : SLP_SUS# is ignored in Non-DSx systems
3VDUAL , VCC3_PCH,VCC1_0_PCH
PCH Prim Rails Note 2 : See Rail-to-Rail Power Sequencing Requirement section for details on PCH prime rail-to-rail power and power down dependencies
4.
RSMRST# tPCH03 : VccPrimary stable to RSMRST# high . Note 4 : For a non-DeepSx system DSW_PWROK and RSMRST# go high at the same time
RSMRST# de-assertion to SUSPWRDNACK valid
tPLT01
SUSPWRDNACK Valid
SUSCLK Running

SUS_ACK# Note 5 : For a non-DeepSx system SUS_ACK# will rise with prime voltage rail powering
PWRBTN#
Note 6 : Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

SLP_A# Note 7 : On first exit from G3, SLP_A# de-asserts with SLP_S3# de-assertion
Platform VCCASW 5. tPCH09 SLP_A# high to PCH assuming ASW rails are stable

SLP_S5# Note 10 : Delay between SLP_S5#, SLP_S4#, and SLP_S3# exaggerated for drawing purposes.
SLP_S4#

SLP_S3#
VccST_VccPLL
VccST, VccPLL
Note 11 : VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.
tCPU04 : VCCST ramping and stable before VCCSTG
VccSTG Note 11
VPP_25V
VPP Note 12 : Only required with LPDDR3 and DDR4 memory configurations

Dept : #41B研發服務部 By: P.4
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