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KBL S Flow Diagram for SYS_PWROK/PCH_PWROK Generation
SVID Transaction
SLP_S3# CPU SVID SVID
S4 PWM KBL S
VRs VR_ON
EN PGD VR_READY
VCCST_PWRGD
VCCST SIO Level
PwrGate Delay(ms) Shifter
EN PGD N_PCH_VRMPWRGD
SYS_PWROK
VCCIO V3.3S PROCPWRGD
VR
EN PGD
PLTRST#
Other
S0 VRs SIO PWROK1
EN PGD PWOK Delay
(ms) PCH_PWROK
ATX PSU Negative
VM Edge PCH
PWOK
EN PGD Detect
SLP_S3#
SLP_S4#
Dept : #41B研發服務部 By: P.4
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