Page 47 - Z270X-Gaming 7

KBL Timing Diagram for G3 to S0/M0 [Non-Deep Sx Platform]/2
PROCPWRGD Assertion
tCPU１1 ：VCCPLL stable before PROCPWRGD
VccST_VccPLL
VccST, VccPLL Note 11 : VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization.
tCPU04 ：VCCST ramping and stable before VCCSTG
Note 11
VccSTG tCPU00：VCCST, VCCSTG ramped and stable to VccST_PWRGD assertion VPP_25V
VPP Note 12 : Only required with LPDDR3 and DDR4 memory configurations
tCPU03 : VDDQ ramping and stable before VCCST, VCCSTG stable
tCPU01 : VDDQ ramped and stable to VccST_PWRGD assertion VDDQ
VDDQ, VccPLL_OC Note 13 : VDDQ must ramp after VPP on DDR4 and LPDDR3 based systems, thus VDDQ may ramp up

after SLP_S3# de-assertion due to VR ramp timing and configuration VCCIO
VCCIO tCPU0５ VDDQ ramping and stable before VCCSA/ VCCIO ramps
tCPU１０ ：VCCIO stable before PROCPWRGD VCCSA
VCCSA Note 1４：VCCIO, VCCSA must ramp after VccST, VccSTG, and VDDQ have completed their ramps. If
VCCSTG and VCCIO supplies are merged together as a single supply, VCCSA must ramp after VccST,
DDR_VTT
VTT VccSTG/VCCIO, and VDDQ have completed their ramps
tCPU18 : DDR_VTT_CNTL assertion to DDR VTT supplied ramped and stable
DDR_VTT_CNTL tCPU19 : VccST_PWRGD assertion to DDR_VTT_CNTL asserted

VDDQPWRGOOD
IMVP VR_READY

Platform S0 Rails
tPLT04 :ALL_SYS_PWRGD assertion to PCH_PWROK. This timing must be controlled on
ALL_SYS_PWRGD the platform
VCCST_PWRGD N_PCH_VRMPWRGD / CPU_VCCST_PWRGD / Note 17 : VCCST_PWRGD can assert before or equal to PCH_PWROK, but must never lag it

PCH_PWROK tCPU16 : VCCST_PWRGD assertion to PCH_PWROK assertion
PCH Clock Outputs O_PWROK1
tPCH41 : PCH_PWROK high to PCH clock outputs stable
PROCPWRGOOD CPU_PWROK

IMVP VR_ON

tPLT05 : ALL_SYS_PWRGD assertion to SYS_PWROK. This
CPU SVID BUS timing must be controlled on the platform.
SYS_PWROK SYS_PWROK

SUS_STAT#

Dept : #41B研發服務部 By: P.4
6