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Figure 15.7 Use of the Delayed Branch

immediately preceding instruction, then the compiler must refrain from doing the interchange
and instead insert a NOOP. Otherwise, the compiler can seek to insert a useful instruction after
the branch. The experience with both the Berkeley RISC and IBM 801 systems is that the majority
of conditional branch instructions can be optimized in this fashion ([PATT82a], [RADI83]). delayed
load A similar sort of tactic, called the delayed load, can be used on LOAD instructions.

On LOAD instructions, the register that is to be the target of the load is locked by the processor.
The processor then continues execution of the instruction stream until it reaches an instruction
requiring that register, at which point it idles until the load is complete. If the compiler can
rearrange instructions so that useful work can be done while the load is in the pipeline, efficiency
is increased.

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