Page 7 - 8237A (1)

8237A

With Rotating Priority in a single chip DMA system, Current Word RegisterÐEach channel has a 16-
any device requesting service is guaranteed to be bit Current Word Count register. This register deter-
recognized after no more than three higher priority mines the number of transfers to be performed. The
services have occurred. This prevents any one actual number of transfers will be one more than the
channel from monopolizing the system. number programmed in the Current Word Count reg-
ister (i.e., programming a count of 100 will result in
Compressed TimingÐIn order to achieve even 101 transfers). The word count is decremented after
greater throughput where system characteristics each transfer. The intermediate value of the word
permit, the 8237A can compress the transfer time to count is stored in the register during the transfer.
two clock cycles. From Figure 11 it can be seen that When the value in the register goes from zero to
state S3 is used to extend the access time of the FFFFH, a TC will be generated. This register is load-
read pulse. By removing state S3, the read pulse ed or read in successive 8-bit bytes by the micro-
width is made equal to the write pulse width and a processor in the Program Condition. Following the
transfer consists only of state S2 to change the ad- end of a DMA service it may also be reinitialized by
dress and state S4 to perform the read/write. S1 an Autoinitialization back to its original value. Auto-
states will still occur when A8–A15 need updating initialize can occur only when an EOP occurs. If it is
(see Address Generation). Timing for compressed not Autoinitialized, this register will have a count of
transfers is found in Figure 14. FFFFH after TC.
Address GenerationÐIn order to reduce pin count, Base Address and Base Word Count RegistersÐ
the 8237A multiplexes the eight higher order ad- Each channel has a pair of Base Address and Base
dress bits on the data lines. State S1 is used to out- Word Count registers. These 16-bit registers store
put the higher order address bits to an external latch the original value of their associated current regis-
from which they may be placed on the address bus. ters. During Autoinitialize these values are used to
The falling edge of Address Strobe (ADSTB) is used restore the current registers to their original values.
to load these bits from the data lines to the latch. The base registers are written simultaneously with
Address Enable (AEN) is used to enable the bits their corresponding current register in 8-bit bytes in
onto the address bus through a three-state enable. the Program Condition by the microprocessor.
The lower order address bits are output by the These registers cannot be read by the microproces-
8237A directly. Lines A0–A7 should be connected sor.
to the address bus. Figure 11 shows the time rela-
tionships between CLK, AEN, ADSTB, DB0–DB7 Command RegisterÐThis 8-bit register controls
and A0–A7. the operation of the 8237A. It is programmed by the
microprocessor in the Program Condition and is
During Block and Demand Transfer mode services, cleared by Reset or a Master Clear instruction. The
which include multiple transfers, the addresses gen- following table lists the function of the command
erated will be sequential. For many transfers the bits. See Figure 6 for address coding.
data held in the external address latch will remain
the same. This data need only change when a carry Mode RegisterÐEach channel has a 6-bit Mode
or borrow from A7 to A8 takes place in the normal register associated with it. When the register is being
sequence of addresses. To save time and speed written to by the microprocessor in the Program
transfers, the 8237A executes S1 states only when Condition, bits 0 and 1 determine which channel
updating of A8–A15 in the latch is necessary. This Mode register is to be written.
means for long services, S1 states and Address
Strobes may occur only once every 256 transfers, a Request RegisterÐThe 8237A can respond to re-
savings of 255 clock cycles for each 256 transfers. quests for DMA service which are initiated by soft-
ware as well as by a DREQ. Each channel has a
request bit associated with it in the 4-bit Request
REGISTER DESCRIPTION register. These are non-maskable and subject to pri-
oritization by the Priority Encoder network. Each reg-
Current Address RegisterÐEach channel has a ister bit is set or reset separately under software
16-bit Current Address register. This register holds control or is cleared upon generation of a TC or ex-
the value of the address used during DMA transfers. ternal EOP. The entire register is cleared by a Reset.
The address is automatically incremented or decre- To set or reset a bit, the software loads the proper
mented after each transfer and the intermediate val- form of the data word. See Figure 5 for register ad-
ues of the address are stored in the Current Address dress coding. In order to make a software request,
register during the transfer. This register is written or the channel must be in Block Mode.
read by the microprocessor in successive 8-bit
bytes. It may also be reinitialized by an Autoinitialize
back to its original value. Autoinitialize takes place
only after an EOP.

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