Page 115 - Handout Digital Electronics

14.2 Negative edge clock transition
The negative edge clock pulse transition is also known as the falling edge transition, leading edge or the
1 to 0 transition. The negative edge and positive transition principle of operation is basically the same.

Figure 49: Negative edge transition

Negative edge triggered flip flop symbol

The clock in the negative edge transition has an inversion bubble to show that it is activated by a low-
level signal.

14.3 Flip flop state diagrams
Flip flop state diagrams are used in the design of state diagrams. The state diagrams show the transitions
from one state to the next as dictated by the flip flop inputs and the present states. In a state diagram, a
state is shown by a circle. The binary number inside the circle defines the present state. Transition from
one state to the next is shown by a directed line and the present inputs that cause the transitions are
labelled on the directed line. Where the present state is the same as the next state, a directed line is
drawn connecting the circle with itself and labelled the present inputs, for example in the SR state table,
S = R = 0, the next state is the same as the present state. When S = 1 and R = 0, transition is from state Q
= 0 to state Q = 1. When S = 0 and R =1, transition is from state Q = 1 to state Q = 0. (see figure 50
below).

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