Page 111 - Handout Digital Electronics

13.4 The D (data) Flip flop
The D flip flop is the best way to avoid the ambiguous case. This flip flop has one data input line and the
D input to the upper NAND gate is the complement to the D input of the lower NAND gate. In this way
the case of both inputs being logical ones (1s) does not arise. (See logic diagram below in figure 45.

Figure 45: D flip flop implemented on NAND gates.

The D flip flop can also be implemented on AND and NOR gates. The D flip flop operates as follows:

• When the clock C = 1 and D = 1, Q = 0 and Q = 1

• When C = 1 and D = 1, Q =1 and Q = 0

D flip flop state table

C D Q Q
1 0 0 1
1 1 1 0

The D flip flop is the simplest in terms of its operation and in this module, it is used to illustrate the
operation of most complex logic circuit diagrams.

Figure 46: D flip flop showing simulated signals propagation when C =1, D =1.

The expected output is Q =1 and Q . So, what one needs to know is that when the clock(C) = 1, the value
at D is the one that will be displayed at the output.

D flip flop implemented on AND and NOR gates

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