Page 107 - Handout Digital Electronics

Figure 39: Clocked JK flip flop implemented on NAND gates only.
The implementation is like that of the clocked JK implemented on AND and NOR gates but note that the
feedback connections. Unlike in the clocked flip flop implemented on AND NOR gates, in the clocked
flip flop implemented on NAND gates, the output of the upper NAND gate is connected to the inputs of
the lower NAND gate, and the output of the lower NAND gate is connected to the input lines of the
upper NAND gate.

Truth table

C J K Q Q Name

1 0 0 0 1 No change
1 0 1 0 1 Reset (clear to 0)
1 1 0 1 0 Set to 1 (store)
1 1 1 0 1 Toggle

Operation of the clocked JK flip flop implemented on NAND gates only

The truth table above summarizes the operation of the clocked JK flip flop implemented on NAND gates
only. Just like in the clocked JK flip flop implemented on AND and NOR gates, the feedback is only
used when C =1, J = 1, and K = 1.

In the clocked JK flip flops implemented on NAND gates only, when the input combination C = 1, J = 1
and K = 1, arises, the outputs of the previous states and present inputs are used to generate the present
state. For example, consider the clocked JK flip flop below with simulated signals:

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