Page 108 - Handout Digital Electronics

Figure 40: JK flip flop implemented on NAND gates showing simulated signals

Assume the previous outputs were Q = 1 and Q = 0. The 1 is from the previous output of the upper
NAND gate and is fed back to the lower NAND. The zero (0) is from the previous output of the lower
NAND gate and is propagated to the inputs of the upper NAND gate. The inputs to the upper NAND
gates are now J = 1, C = 1 and feedback (the previous state =1. These are passed on through the upper

NAND gate. The result if simulation is Q = 0 and not Q ( Q ) = 1. Although JK flip flop is an
improvement on the clocked SR flip-flop because of the elimination of the ambiguous case (invalid
inputs), it still suffers from timing problems called “race” if the output Q changes state before the timing
pulse of the clock input has time to go “OFF”. This causes the flip flops to toggle more than once.
To
avoid this (toggling more than once), the timing pulse period (T) must be kept as short as possible by
using high frequency. This is sometimes not possible with modern TTL IC‟is the much improved. The
Master-Slave JK Flip-flop was developed to eliminate the problem of toggling more than once.

13.2 The JK Master-Slave Flip Flop

The JK master- slave flip flop was developed to eliminate the problem of toggling more than once which
is associated with the JK flip flop. This flip flop is made up of two flip flops in one, the master which is
used to‟ manufacture‟ the contents and the slave which is used to store the „manufactured‟ contents. The
JK master-slave flip flop logic circuit is shown below:

Figure 41: JK Master- Slave Flip Flop implemented on NAND gates

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