Page 105 - Handout Digital Electronics

LECTURE 13 SEQUENTIAL LOGIC CIRCUITS
13.1 The Clocked JK flip flop
The clocked JK flip flop is a modification of the SR clocked flip flop. This flip flop was designed to
eliminate the SR flip flop ambiguous case. (See logic circuit below). The JK flip flop was designed by
Jack Kilby and gets its name from the initials of his first and last names.

Figure 37: Clocked JK flip flop implemented on AND and NOR gates

The letters J and K do not stand for anything but are used to distinguish the JK flip flop from the SR flip
flop. J = S and K = R. Note that the above flip flop is implemented using the AND and NOR gates.

As can be seen from the above logic circuit, the outputs of Q and Q are fed back to the AND gates.
This is the only modification which is absent in the clocked SR flip flop. The J input is used to set the
flip flop into state one (store) when it is equal to one (1) and the K input is used to reset/clear to zero
when it is equal to 1.

The feedback lines are only used in cases when C = 1, J = 1 and K = 1 otherwise they are not used. From
the above statement the JK flip flop operates like the SR flip except when C =1, J = 1 and K =1.

The clocked JK flip flop operates as follows:

When C = 1, J = 0, K = 0, Q = 0, Q = 1

When C =1, J = 0, K = 1, Q = 0, Q = 1

When C = 1, J =1, K = 0, Q = 1, Q = 0

When C =1, J = 1, K = 1, Q = 0 and Q = 1

The feedback complements the previous state. The operations of the JK flip flop can the summarized by
the state table as shown. The introduction of the feedback eliminated the ambiguous case since it will
always toggle (complement) the previous state whenever J = K= 1.

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