Page 106 - Handout Digital Electronics

C J K Q Q Name
1 0 0 0 1 No change
1 0 1 0 1 Reset (clear to 0)
1 1 0 1 0 Set to 1 (store)
1 1 1 0 1 Toggle

Explanation of the toggle process in the JK flip flop implemented on AND and NOR gates When C
=1, J = 1 and K =1, propagate the input values to the outputs of the NOR gates. Take the outputs and
feed them back to the AND gates and propagate the inputs again to the outputs of the NOR gates. These
are now the correct outputs. For example, consider the JK flip flop below with simulated values of the
inputs:

Figure 38: Clocked JK flip flop showing simulated signals

Simulation starts with the Upper AND gate where the JK input is connected. Take J =1, C = 1,
propagate them through the AND gates give a 1, which is passed on to the upper NOR gate, gives a 0 at
the output of the NOR gate which is fed back to the upper AND gate. On the lower AND gate, take the
clock C =1 and K = 1, propagate them through the lower AND gate, gives a 1 at the output which is
passed on to the input of the lower NOR gate and gives a 0 at its output. The 0 is propagated back to the
inputs of the lower AND gate. So, at the upper AND gate, we have feedback = 0, J = 1 and C =1. These
signals are passed through the AND gate and give a 0 at its output. The 0 signal is propagated to
the NOR gate which gives a 1 at the not Q ( Q ) output. The 1 at the not Q ( Q ) output is the final output
at the upper NOR gate. On the lower AND gate, we have C =1, K = 1 and Feedback signal = 0. When
passed through the lower AND gate produces a 0 at its output. The 0 signal is passed on to the lower
NOR gate, together with a 1 from the upper NOR gate.(Note that the output of the upper NOR gate is
also connected to the input of the lower NOR gate. So, a 0 and a 1 through the NOR gate produces a zero

(0). The final outputs are Q = 0 and Q = 1. This is how the ambiguous case was eliminated in the SR
flip flop.

The Clocked JK flip flop can also be implemented on NAND gates only:

For example:

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