Page 4 - Handout Digital Electronics

LECTURER 4 COMBINATIONAL LOGIC CIRCUITS .................................................................................................... 23

4.1. Boolean algebra ................................................................................................................................. 23
4.2 Laws of Boolean algebra ...................................................................................................................... 24

LECTURE 5 TRUTH TABLES ................................................................................................................................... 29
5.1 Introduction ........................................................................................................................................ 29

5.2 Forms of Boolean Expressions .............................................................................................................. 30
5.3 The Sum of Products (SOP) form .......................................................................................................... 31

5.4 The Product of Sums (POS) form .......................................................................................................... 31
LECTURE 6 DIGITAL LOGIC GATES .......................................................................................................................... 35

6.1 Introduction ........................................................................................................................................ 35
6.2 NOT Logic gate ............................................................................................................................... 35

6.3 Buffer ................................................................................................................................................. 35
6.4 The OR Logic Gate ............................................................................................................................... 36

6.5 The AND logic gate .............................................................................................................................. 36
6.6 The NOR logic gate .............................................................................................................................. 37

6.7 The NAND logic gate ............................................................................................................................ 37
6.8 Exclusive OR (XOR) logic gate ............................................................................................................... 38

6.9 Exclusive NOR (XNOR) logic gate .......................................................................................................... 39

6.10 Deriving Boolean functions from truth tables ...................................................................................... 40
7.1 Introduction ........................................................................................................................................ 43

7.3 The Karnaugh Map Method of Minimizing Boolean Functions ............................................................... 44
7.4 Two variable Karnaugh map ................................................................................................................. 45

7.5 Examples of minimizing 2-Boolean variables functions .......................................................................... 46
7.6 Karnaugh Maps Rules used in the Simplification of Boolean Functions ................................................... 47

7.7 The three variable Karnaugh map ......................................................................................................... 48

LECTURE 8 THE TABULAR METHOD ....................................................................................................................... 51
8.1 Introduction ........................................................................................................................................ 51
8.2 Rules of Tabular Method ..................................................................................................................... 51

8.3 Using a chart to remove redundant prime implications ................................................................................... 58
LECTURE 9 COMBINATIONAL LOGIC CIRCUIT BUILDING BLOCKS .......................................................................... 63

9.1 Implementation of Logic Gates ............................................................................................................ 63
9.2 Adders ................................................................................................................................................ 63

. .............................................................................................................................................................................. 64
9.3 Full Adder (FA) .................................................................................................................................... 64