Page 5 - Handout Digital Electronics

9.4 Comparators ....................................................................................................................................... 67

9.5 Comparator for equality ...................................................................................................................... 67

9.6 Full Comparator .................................................................................................................................. 69
10.1 Multiplexers ...................................................................................................................................... 72

10.2 DE multiplexor .................................................................................................................................. 74
LECTURE 11 COMBINATIONAL LOGIC CIRCUIT BUILDING BLOCKS ........................................................................ 81

11.1 Decoders ........................................................................................................................................... 81
11.2 Encoders ........................................................................................................................................... 82

11.3 Priority encoder ................................................................................................................................ 84
LECTURE 12 SEQUENTIAL LOGIC CIRCUITS ............................................................................................................ 87

12.1 Introduction ...................................................................................................................................... 87
12.2 The SR Latch ...................................................................................................................................... 88

LECTURE 13 SEQUENTIAL LOGIC CIRCUITS ............................................................................................................ 94
13.1 The Clocked JK flip flop ...................................................................................................................... 94
13.2 The JK Master-Slave Flip Flop ................................................................................................................. 97

13.3 The T (Toggle) Flip Flop ...................................................................................................................... 98
13.4 The D (data) Flip flop ....................................................................................................................... 100

LECTURE 14 EDGE TRIGGERED FLIP FLOPS ........................................................................................................... 102
14.1 Positive edge transition and negative edge transition ........................................................................ 102

14.2 Negative edge clock transition ......................................................................................................... 103
14.3 Flip flop state diagrams .................................................................................................................... 103

LECTURER 15 SEQUENTIAL CIRCUIT EQUATIONS ................................................................................................ 106
15.1 Typical sequential circuit diagram .................................................................................................... 106

15.3 Full design of a sequential circuit ...................................................................................................... 107
LECTURE 16 BINARY COUNTERS .......................................................................................................................... 111

16.2 Counter Types ................................................................................................................................. 111
16.3 4 –bit Asynchronous binary up counter ............................................................................................ 111

16.4 A 4-bit Asynchronous binary down counter ...................................................................................... 113
LECTURE 17 SYNCHRONOUS BINARY COUNTERS ................................................................................................ 116

17.1 Introduction .................................................................................................................................... 116
17.2 A 4-bit binary synchronous up counter ............................................................................................. 116

17.3 A 4-bit binary synchronous down counter ......................................................................................... 117
17.3 synchronous reversible counters ...................................................................................................... 118

LECTURE 18 COMPUTER REGISTERS .................................................................................................................... 120

5