Page 85 - GIGABYTE Service Manual-v3.0-110101

5.2.8 SMBDATA or SMBCLK Fail

Example: Intel
EP45-UD3R identified by:
01. Post code C1.

02. Signal measure noise on SMBDATA and SMBCLK
03. DU8 IT8268R swaps ok.

Figure 5-12: SMBDATA or SMBCLK Fail Check

Signal Explanation:
01. The ICH9 provides a System Management Bus (SMBus) host controller as well as a

SMBus Slave Interface. The host controller provides a mechanism for the processor to
initiate communications with SMBus peripherals (slaves). SMBus is also capable of
operating in a mode in which it can communicate with I2C compatible devices.

02. The programming model of the host controller is combined into two portions: a PCI
configuration portion and a system I/O mapped portion. All static configurations, such
as the I/O base address, are done via the PCI configuration space. The ICH9 SMBus
host controller checks for parity errors as a target. If an error is detected, the detected

parity error bit in the PCI Status Register is set. If bit 6 and bit 8 of the PCI Command
Register are set, SERR # is generated and the signaled SERR# bit in the PCI Status
Register is set.

03. The SMBus host controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data and
optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it generates an SMI# or interrupt,

if enabled.

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