Page 364 - FUNDAMENTALS OF COMPUTER

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364 Fundamentals of Computers NPP

Computer Fundamentals H$å߶yQ>a ’§$S>m‘|Q>b

4.14 System Bus 4.14 {gñQ>_ ~g
A bus is a group of parallel wires between g_mZm§Va dm`am| H$m dh g_yh Omo CPU, _o_moar VWm
CPU, memory and IO devices for carrying in- BZnwQ>-AmCQ>nwQ> Ho$ ~rM _| {dÚwV {g¾bm| Ho$ ê$n _|
formation in the form of electrical signals. The
system bus is a combination of three types of OmZH$mar àdm{hV H$aVm h¡, ~g H$hbmVm h¡ Ÿ& {gñQ>_
buses as listed below: ~g VrZ Vah H$s ~gm| go ~Zr hmoVr h¢ …
1. Address Bus 1. ES´>og ~g
2. Data Bus 2. S>mQ>m ~g
3. Control Bus 3. H§$Q´>mob ~g

Address Bus ES´>og ~g
Address bus refers to the group of wires Bg ~g na _o_moar `m {H$gr BZnwQ>-AmCQ>nwQ> H$m
which are used to carry the address of memory ES´>og AmVm h¡Ÿ& `h h_oem EH$ {Xer` hmoVm h¡ Š`m|{H$ `h
or input output device. The address bus is
unidirectional because it always runs from CPU h_oem grnr`y go Xygar `w{º$`m| H$s Amoa OmVm h¡Ÿ& grnr`y
to other devices. There is no address of CPU. It H$m H$moB© ES´>og Zht hmoVm ~pëH$ `h Xygar `wpŠV Ho$ ES´>og,
is the CPU which selects any input-output ~g na S>mbH$a CÝh| MwZVm h¡Ÿ&
device or a memory location.
The number of address lines in the address _mBH«$moàmogoga na pñWV ES´>og dm`am| H$s g§»`m go
bus indicates the memory addressing capability CgHo$ Hw$b _o_moar H$s j_Vm nVm MbVr h¡Ÿ& O¡go 8085
of a micro-processor. For example, in micropro- _| 16-{~Q> H$m ES´>og ~g h¡ Ÿ& AV… BgH$s j_Vm 2 =
16
cessor 8085 16- Address lines are there. There-
16
fore it can address 2 = 64K of memory. On the 64 K _o_moar h¡ VWm 8086/88 _| 20 {~Q> H$m ES´>og h¡
20
other hand 8086/8088 has 20 address lines to AV… BgH$s j_Vm 2 = 1M _o_moar H$s h¡Ÿ&
address 2 = 1M of memory address.
20
Data Bus S>mQ>m ~g
Data bus refers to the group of parallel S>oQ>m ~g S>oQ>m `m BÝñQ´>ŠeZ Ho$ àdmh Ho$ {bE n¡aobb
wires for the flow of data or instruction. The dm`g© Ho$ EH$ g_yh H$m gÝX^© XoVm h¡Ÿ& S>oQ>m `m BÝñQ´>ŠeZ
Data or instruction flows between IO, memory,
and CPU. Data bus is bidirectional. For ex- IO _o_moar VWm CPU Ho$ ~rM àdm{hV hmoVo ahVo h¢Ÿ& CXmhaU
ample, when data is fetched by CPU from Ho$ {bE, O~ S>oQ>m H$mo CPU Ûmam _o_moar _| bm`m OmVm h¡
memory it is called read operation. Write op- Vmo Bgr arS> Am°naoeZ H$hm OmVm h¡Ÿ& amBQ> Am°naoeZ ^r
eration is also possible. The directions for the gå^d h¡Ÿ& S>oQ>m Ho$ àdmh H$s {Xem arS> VWm amBQ> Am°naoeZ
flow of data will be opposite to each other in _| EH$-Xygao Ho$ {dnarV hmoJrŸ& S>mQ>m ~g _| CnpñWV
read and write operation. The number of data
lines available in the data bus decides the pro- bmB©Zm| H$s g§»`m go CPU H$s àmoJ«m_ {H«$`mÝd`Z H$s J{V
gram execution speed of the CPU. For example H$m nVm MbVm hmoVm h¡Ÿ& O¡go 8085 _| 8 {~Q> H$m S>mQ>m
8085 has 8 data lines, therefore it can read or ~g h¡Ÿ& AWm©V² `h EH$ g_` _| 8-{~Q> H$s g§»`m {bI
write only 8 bit data at a time. While micropro- `m n‹T> gH$Vm h¡Ÿ& O~{H$ _mBH«$mo àmogoga 8086 _| 16-