Page 15 - rise 2017

Stage 3:
1. Filter circuit is used to reduce the ripple of the waveform and the content of the harmonic.

Stage 4:
1. Non-linear load also create the content of harmonics in the output value depending on the
impedance.

Method 3: Power Factor Correction (PFC) by Using Bridgeless Topology and Interleaved
Converter
For the third analysis, the method for Power factor Correction is by using two converters in which this
method neglects the used of the rectifier circuit. In this method, the first converter is referring to the
Bridgeless topology and the second converter is by using an interleaved topology. This method is
proposed due to its capability to overcome the disadvantages of the second method.

Stage 1 Stage 2 Stage 4
Stage 3

Figure 4: Equivalent circuit of Power Factor Correction method (PFC) by using Bridgeless Topology
and Interleaved Converter

Stage 1:
1. Pulse voltage was used to create a harmonic content and as an analysis for one complete cycle
waveform.
2. Pulse voltage duration set to 20ms due to setting for one period frequency is equivalent to
50Hz.
3. Voltage setting ranged from 0 to 20V used as most of home electronics appliances uses
DC supply within 10V to 20V.
4. The function of inductor as an input current sensing, which sense the current flow to the
Bridgeless topology circuit.
5. The functions of four inductors are to boost up the current flow from the input.

Stage 2:
1. Bridgeless topology is used as a power factor correction method.
2. The function of parallel components between diode and MOSFET to reduce the conduction
losses during the switching operations [8].

Stage 3:
1. Interleaved topology is used to remain constant the value of power factor.