Page 236 - Mechatronics with Experiments

222 MECHATRONICS
and data can be accessed simultaneously. The PIC 18F452 contains a RISC processor. This
particular RISC processor has 75-word basic instruction set.
PIC 18F452 chip is compatible with clock speeds between 4 MHz and 40 MHz. The
clock speed is determined by two factors:
1. hardware: the external crystal oscillator or ceramic resonators along with a few
capacitors and resistors,
2. software: configuration register settings to select the operating mode of the processor.

PIC 18F452 supports up to 31 levels of stack, which means up to 31 subroutine calls
and interrupts can be nested (Figure 4.8) for the low priority interrupts. Stack space in the
memory holds the return address from the function calls and from interrupt service routines.
Stack space is neither part of the program memory nor data memory.
The program counter (PC) register is 21-bits long (Figure 4.7). Hence, the address
space for program memory can be up to 2 MB. PIC 18F4431 is flash memory based and
has 16 KB of FLASH program memory (addresses 0000h through 6FFFh) which is 8 K
of two-byte (single-word) instruction space (Figure 4.7). Data memory is implemented in
RAM and EEPROM. Data RAM (static RAM, (SRAM)) has 4096 (4 KB) bytes of space
via the 12-bit data bus address, of which 768 bytes is implemented as SRAM, and 256
bytes implemented as EEPROM on PIC 18F4431. The address space F60h through FFFh
(160 bytes) is reserved for Special Function Registers (SFR) each of which is an 8-bit
register. SFRs are used to configure and control the operation of the core CPU and I/O
peripherals. It is through accessing these registers (160 8-bit SFRs), that practically all
of the I/O operation of the microcontroller is accomplished. The rest of the data memory
can be considered as General Purpose Registers, which are used as a scratch pad for data
storage.
In C-language using a C18 compiler, using the “rom” directive, data variables can
be explicitly directed to be allocated in program memory space if data memory space is
not sufficient for a given application. Similarly, the “ram” directive in data declarations
allocates memory in data memory.

rom char c ;
rom int n ;

ram float x ;

Some of the important locations in the program memory map are as follows:

1. The RESET vector is at address 0x0000h.
2. The high priority interrupt vector is at address 0x0008h.
3. The low priority interrupt vector is at address 0x0018h.

The RESET condition is the startup condition of the processor. When the processor is
RESET, the program counter content is set to 0x0000h, hence the program branches to this
address to get the address of the instruction to execute. The C-compiler places the beginning
address of the main() function at this location. Hence, on RESET, the main() function of
a C-program is where the program execution starts. The source of RESET can be:
1. Power-on-reset (POR): when an on-chip V DD rise is detected, a POR pulse is gen-
erated. On power-up, the internal power-up timer (PWRT) provides a fixed time-out
delay to keep the processor in RESET state so that V DD rises to an acceptable and
stable level. After the PWRT time-out, the oscillator startup timer (OST) provides
another time delay of 1024 cycles of oscillator period.