Page 237 - Mechatronics with Experiments

MICROCONTROLLERS 223
Data bus<8>
PORTA
RA0/AN0
Table pointer Data latch
21 RA1/AN1
8 8 8 Data RAM RA2/AN2/Vref–
inc/dec logic (up to 4K RA3/AN3/Vref+
21 address rearch) RA4/T0CKI
Address latch RA5/AN4/SS/LVDIN
RA6
Address latch 21 Pclatu Pclath 12 (2)
Program memory PCU PCH PCL Address <12>
(up to 2 mbytes) PORTB
Program counter 4 12 4
Data latch BSR FSR0 Bank0,F RB0/INT0
RB1/INT1
FSR1 RB2/INT2
31 level stack FSR2 [1]
12 RB3/CCP2
RB4
RB5/PGM
16 inc/dec
Decode logic RB6/PGM
Table latch RB7/PGM
8
ROM latch PORTC
RC0/T1OSO/T1CKI
RC1/T1OSOI/CCP2 [1]
Instruction RC2/CCP1
register RC3/SCK/SCL
RC4/SDI/SDA
8 RC5/SDO
Instruction
decode & RC6/TX/CK
control PRODH PRODL RC7/RX/DT
OSC2/CLKO 3
OSC1/CLKI Power-up 8 x 8 Multiply PORTD
timer 8 RD0/PSP0
T1OSCI Timing Oscillator BIT OP WREG RD1/PS1
T1OSCO generation start-up timer 8 8 8 RD2/PSP2
Power-on RD3/PSP3
reset 8 RD4/PSP4
RD5/PSP5
4×PLL Watchdog ALU<8> RD6/PSP6
timer RD7/PSP7
Brown-out
Precision reset 8 PORTE
voltage
reference Low voltage
MCLR programming RE0/AN5/RD
In-circuit RE1/AN6/WR
Vdd,Vss
debugger
RE2/AN7/CS
Timer 0 Timer 1 Timer 2 Timer 3 A/D converter
Master
CCP 1 CCP 2 synchronous Addressable Parallel slave port Data EEPROM
USART
serial port
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
FIGURE 4.7: Block diagram of the PIC 18F452: registers, bus, peripheral devices, and ports
(Fig.1-2 from PIC 18Fxx2 Data Sheet). Reproduced with permission from Microchip Technology,
Inc.
2. MCLR reset during normal operation or during SLEEP: the MCLR input pin can be
used to RESET the processor on demand.
3. Brown-out reset (BOR): when the V DD voltage goes below a specified voltage level
for more than a certain amount of time (both parameters are programmable), the BOR
reset is activated automatically.