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224 MECHATRONICS
4. Watch dog timer (WDT) reset: WDT can be used to reset the processor if it times-out
during normal operation in order to clear the state of the processor, or it can also
be used to wake-up the processor from SLEEP mode. In WDT reset during normal
operation, the program counter is initialized to 0x0000h, whereas in WDT wake-up
mode, the program counter is incremented by 2 to continue to the instructions where
it was left.
5. RESET instruction, stack full and stack underflow conditions result in software
initiated reset conditions.

When PIC 18F452 executes a SLEEP instruction, the processor is held at the beginning of
an instruction cycle. The processor can be woken-up from SLEEP mode by either external
RESET, Watchdog Timer Reset or an external interrupt.

4.3.2 Microprocessor Software
Addressing Modes Data memory space in PIC 18F452 is accessed by a 12-bit long
address space, which means that it is 4096 bytes long. This space is organized as 16 banks
of 256 bytes of memory (Figure 4.8). Banks 0–14 are used as General Purpose Registers
(GPRs). GPRs can be used for general data storage. The upper half of bank 15 (F80h-
FFFh) is used as Special Function Registers (SFR). Lists of all registers of PIC 18F452
are provided in the PIC 18F452 Users’ Manual. SFRs are used for configuration, control,
and status information of the microcontroller. Most features of the microcontroller are
configured by properly setting the SFRs. EEPROM data memory space is 256 bytes and is
accessed indirectly through SFRs. There are four SFRs involved in accessing EEPROM:
EECON1, EECON2, EEDATA, and EEADR. EEDATA and EEADR registers are used to

PC<20:0> BSR<3:0> Data memory map
CALL, RCALL, RETURN, 21
RETFLE, RETLK = 0000 00h Access RAM 000h
07Fh
Stack level 1 Bank 0 FFh GPR 080h
.
.
0FFh
.
= 0001 00h 100h
Stack level 31 Bank 1 GPR
FFh 1FFh
RESET VECTOR 0000h = 0010 00h 200h
Bank 2 GPR
High priority interrupt vector 0008h FFh 2FFh
300h
Low priority interrupt vector 0018h = 0011 Bank 3 00h GPR
FFh 3FFh
400h
= 0100
Bank 4 GPR Access bank
4FFh 00h
= 0101 00h 500h Access RAM low 7Fh
On-chip Bank 5 GPR Access RAM high 80h
program memory FFh 5FFh (SFR’s) FFh
User memory space When a = 0,
600h
Unused
7FFFh = 0110 Bank 6 Read ‘00h’ the BSR is ignored and the
to
= 1110
8000h Bank 14 access bank is used.
The first 128 bytes are general
purpose RAM (from bank 0).
The second 128 bytes are
EFFh special function registers
00h F00h
Read ‘0’ = 1111 Unused E7Fh (from bank 15).
Bank 15 F80h
FFFh SFR FFFh
When a = 1,
the BSR is used to specify the
1FFFFFh RAM location that the
200000h instruction uses.
(a) (b)
FIGURE 4.8: Memory map of PIC 18F452: (a) program memory map (Fig. 4.2 from PIC 18Fxx2
Data Sheet), (b) data memory map (Fig. 4.7 from PIC 18Fxx2 Data Sheet). Reproduced with
permission from Microchip Technology, Inc.