Page 249 - Mechatronics with Experiments

MICROCONTROLLERS 235
Watch Dog Timers A watch dog timer (WDT) is a hardware timer, which is used to
reboot or take a predefined action if it expires. The watch dog timer keeps a “watch eye”
on the system performance. If something gets stuck, the watch dog timer can be used to
reset everything. A watch dog timer is essential in embedded controllers. The WDT counts
down from a programmable preset value. If it reaches zero before the software resets the
counter to preset value, it is assumed that something is stuck. Then the processor’s reset line
is asserted. The time-out period can be programmed to a value between 4 ms to 131.072 s.
The watchdog timer (WDT) on the PIC chip is an on-chip RC oscillator. It works
even if the main clock of the CPU is not working. WDT can be enabled/disabled, and
the time-out period can be changed under software control. When the WDT times-out, it
generates a RESET signal which can be used to restart the CPU or wake-up the CPU from
SLEEP mode. There are three registers involved in configuration and use of WDT on PIC
18F452 (and PIC 18F4431): CONFIG2H, RCON, WDTCON. If CONFIG2H register bit
0 (WDTEN bit) is 1, WDT cannot be disabled by other software. If this bit is cleared, then
WDT can be enabled/disabled by WDTCON register, bit 0 (1 for enable, 0 for disable).
When WDT times-out, RCON register bit 3 (TO bit) is cleared. The time-out period is
determined in hardware, and extended by post-scaler in software (CONFIG2H register,
bits 3:1).

4.4 INTERRUPTS

4.4.1 General Features of Interrupts
An interrupt is an event which stops the current task the microprocessor is executing, and
directs it to do something else. And when that task is done, the microprocessor resumes
the original task. An interrupt can be generated by two different sources: 1. hardware inter-
rupts (external), 2. software (internal) generated interrupt with an instruction in assembly
language, such as INT n.
When an interrupt occurs, the CPU does the following:
1. Finishes currently executing statement.
2. Saves the status, flags, and registers in the stack so that it can resume its current task
later.
3. Checks the interrupt code, looks at the interrupt service table (vector) to determine the
location of the interrupt service routine (ISR), a function executed when the interrupt
occurs.
4. Branches to the ISR and executes it.
5. When ISR is done, restores the original task from the stack and continues.

When an interrupt is generated, the main task stops after some house-keeping tasks,
and the address location of the ISR for this interrupt needs to be determined. This infor-
mation is stored in the interrupt service vector. The table has default ISR addresses. If you
want to assign a different ISR address (or name) for an interrupt number, the old address
should be saved, then a new ISR address should be written. Later, when the application
terminates, the old ISR address should be restored.
In a given computer control system, there can be more than one interrupt source
and they may happen at the same time. Therefore, different interrupts need to be assigned
different priority levels to determine which one is more important. Higher priority inter-
rupts can suspend lower priority interrupts. Therefore, nested interrupts can be generated
(Figure 4.14).