Page 239 - FUNDAMENTALS OF COMPUTER
P. 239
NPP
NPP Number System, Boolean Algebra and Logic Circuits 239
by putting a bubble. But to cancel a bubble put {Zîà^mdr H$aZo Ho$ {bE OR JoQ> Ho$ BZnwQ> na ^r EH$
one more bubble at the input of OR Gate. The ~~b bJmEŸ& Bg Vah EH$ ~~ëS> OR JoQ> àmßV hmoJmŸ&
resulting circuit contains three NAND, One `h ^r NAND Ho$ Vwë` h¡Ÿ& NOT Ho$ ñWmZ na em°Q>}S>
bubbled OR and one NOT Gate as shown : NAND ~Zm`m Om gH$Vm h¡ …
A B C
C
F
The NOT Gate is equivalent to Shorted NOT JoQ>, em°Q>}©S> NAND Ho$ Vwë` h¡, ~~ëS> OR,
NAND, the bubbled OR is equivalent to NAND Ho$ Vwë` h¡Ÿ& AV: NAND-NAND
NAND. Therefore the NAND-NAND imple- Bpåßc_oÝQ>oeZ Bg àH$ma hmoJm:
mentation is as follows:
A B C
C
F
(ii) NOR Implementation: It is easier and eco- (ii) NOR Bpåßb_|Q>oeZ: hoVw POS ê$n boZm C{MV hmoJm
nomical to take POS Form for NOR-NOR ³¶m|{H$ ¶h gab d gñVm h¡, Omo Bg àH$ma h¡:
implementation:
F = (A + B ) (A. + C ) (B. + C )
