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246 Fundamentals of Computers NPP
Implementation using Universal Gates `y{Zdg©b JoQ>m| H$s ghm`Vm go Bpåßb_|Q>oeZ
NAND and NOR gates are called Univer- NAND Am¡a NOR JoQ²>g H$mo `y{Zdg©c JoQ²>g H$hm
sal Gates. Therefore we have to perform two OmVm h¡Ÿ& AV- h_| Xmo Bpåßc_|Q>oeZ H$aZm hmoJm:
implementations:
(i) NAND-NAND Implementation.
(ii) NOR-NOR Implementation.
Now Consider one by one. A~ EH$-EH$ H$aHo$ {dMma H$aVo h¢&
(i) NAND-NAND Implementation: (i) NAND-NAND Bpåßb_|Q>oeZ:
Use SOP form A.B A.C+ SOP ê$n boZo na A.B A.C+
Draw Logic Circuit using Basic Gates: _yb^yV JoQ>m| go Vm{H©$H$ n[anW ~ZmB`o:
A B C
B
F
Convert AND Gates into NAND Gates. gmao AND JoQ>m| H$mo NAND _| ~Xbmo Ÿ& EH$ ~~ëS>
One Bubbled OR Gate is obtained: OR JoQ> ^r àmßV hmoJm-
A B C
B
F
Replace NOT Gates with shorted NAND A~ NOT JoQ> Ho$ ñWmZ na em°Q>}S> NAND VWm
and bubbled OR Gate with NAND Gate. The ~~ëS> OR JoQ> Ho$ ñWmZ na NAND ~ZmZo na n[aUm‘r
resulting circuit will contain NAND-NAND n[anW ‘| H$odb NAND JoQ> h¡…
Gates only:
