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                   308                         Fundamentals of Computers                           NPP


                   Combinational Logic Circuits               H$m°på~ZoeZb bm°{OH$ g{H©$Q>

                      Combinational Logic Circuits are those in   H$m°på~ZoeZb Vm{H©$H$ n[anW do hmoVo h¢ {OZHo$ dV©_mZ
                  which  the  present output depends upon  the  AmCQ>nwQ>, dV©_mZ BZnwQ> na {Z^©a H$aVo h¢Ÿ& n[anW H$s nwamZr
                  present inputs only. It has nothing to do with
                  previous output. Various combinational logic  AdñWmAm| go `o à^m{dV Zht hmoVo h¢Ÿ& `o n[anW H§$ß`yQ>a Ho$
                  circuits work as building blocks of computer  _yc^yV Ad`d hmoVo h¢Ÿ& `hm± BÝh| g_Pm`m J`m h¡Ÿ&
                  circuit. These are explained in this chapters.
                   3.42 Half Adder                            3.42 hm\$ ES>a
                      Definition: “Half Adder may be defined      n[a^mfm… “Eogm H$m§{~ZoeZb Vm{H©$H$ n[anW Omo Xmo {~Q>m|
                  as the  combinational  logic circuit which  H$m A§H$J{UVr` `moJ àXmZ H$aVm h¡, hm\$ ES>a H$hbmVm h¡Ÿ&”
                  performs arithmetic addition over two bits.”
                      Block Diagram: A block diagram of Half      ãbm°H$ S>m`J«m_… {H$gr hm\$ ES>a Ho$ ãbm°H$ S>m`J«m_
                  Adder can be drawn to show its different inputs  _|§ h_ BZnwQ> VWm AmCQ>nwQ> Xem©Vo h¢Ÿ& My±{H$ `h Xmo {~Q>m|
                  and outputs. Since it adds two bits, therefore it  H$mo Omo‹S>Vm h¡, AV… `hr BgHo$ BZnwQ> hm|JoŸ& {H$Ýht Xmo
                  must have two inputs. The arithmetic addition
                  of two bits gives two bits at the output, one for  {~Q>m| H$mo Omo‹S>Zo na AmCQ>nwQ> _| ^r Xmo {~Q>| àmßV hmoVr
                  sum and  one for  carry.  This  is shown  in the  h¡, EH$ `moJ H$s VWm Xygar hm{gb  H$sŸ& Bgr H$mo {ZåZ
                  block diagram:                              ãbm°H$ S>m`J«m_ _| Xem©`m J`m h¡…


                                              A                              Carry
                                      Input                 Half
                                      Bits                 Adder
                                              B                              Sum

                  Truth Table of Half Adder                   hm\$ ES>a H$s gË`-Vm{bH$m
                      A truth  table for  Half  Adder gives       EH$ hm\$ ES>a H$s gË` Vm{bH$m ~ZmB© Om gH$Vr
                  relationship between inputs and outputs. It can  h¡, Omo BgHo$ {d{^ÝZ BZnwQ>m| VWm AmCQ>nwQ>m| _| g§~§Y
                  be drawn as:
                                                              ~VmE Ÿ&


                                              A        B      Carry     Sum
                                              0        0        0         0
                                              0        1        0         1
                                              1        0        0         1
                                              1        1        1         0

                  Logic Circuit of Half Adder                 hm\$ ES>a H$m Vm{H©$H$ n[anW
                      A Half Adder can be implemented using       EH$ hm\$ ES>a H$m n[anW JoQ>m| H$s ghm`Vm go ~Zm`m
                  logic gates. A visual  inspection of truth table  Om gH$Vm h¡Ÿ& gË`-Vm{bH$m H$mo XoIH$a JoQ>m| H$s nhMmZ
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