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312 Fundamentals of Computers NPP
Logic Circuit for Full Adder \w$b ES>a H$m Vm{H©$H$ n[anW
From the truth table it is clear that the sum gË`-Vm{bH$m go ñnï> h¡ {H$ EH$ VrZ BZnwQ> dmbo
can be provided by one XOR gate having 3- XOR JoQ> Ûmam `moJ àXmZ {H$`m Om gH$Vm h¡Ÿ& bo{H$Z
inputs. But the Carry cannot be provided by
one AND gate. because carry is not equal to EH$ AND JoQ> Carry àXmZ Zht H$a gH$Vm h¡ Š`m|{H$
A.B.C. The K-map technique can be used to A.B.C. Ho$ ~am~a Zht h¡Ÿ& AV… K- _on H$s ghm`Vm go
find the expression for carry: carry H$m ì`O§H$ {ZH$mb gH$Vo h¢…
K-map for Carry Carry H$m K- _on
BC
A 00 01 11 10
0 0 0 1 0
1 0 1 1 1
Solving for three pairs: VrZ no`am| Ho$ {cE hc H$aZo na:
Thus, Carry = A.B + B.C + C.A AV… Carry = A.B + B.C + C.A
Therefore to implement carry we need AV… EH$ VrZ BZnwQ> dmbm OR JoQ> VWm VrZ Xmo
three AND gates and one OR gate. The BZnwQ> dmbo AND JoQ>m| H$s ghm`Vm go Carry H$m
Complete logic circuit of full Adder can be Vm{H©$H$ n[anW ~Zm`m Om gH$Vm h¡Ÿ& \w$b ES>a Ho$ nyU©
drawn as follows:
Vm{H©$H$ n[anW H$mo Bg VarHo$ go ~Zm`m Om gH$Vm h¡…
Full Adder using Half Adders hm\$ ES>a H$s ghm`Vm go \w$b ES>a ~ZmZm
A Full Adder circuit can also be drawn EH$ \w$b ES>a H$mo Xmo hm\$ ES>a H$s ghm`Vm go
using two Half Adders. One Half Adder will
add A and B and another Half Adder will add ~Zm`m Om gH$Vm h¡Ÿ& EH$ hm\$ ES>a A VWm B H$mo Omo‹S>oJm
A⊕ B and C to provide the final sum VWm EH$ AÝ` hm\$ ES>a A ⊕ B VWm C H$mo H$mo Omo‹S>oJm
A⊕ B⊕ C . The final carry is obtained by OR Am¡a A§{V_ `moJ A ⊕ B ⊕ C àXmZ H$aoJmŸ& A§{V_ H¡$ar
ing carries from the two Half Adders. The circuit Xmo hm\$ ES>g© H¡$ar H$mo OR H$aHo$ àmßV {H$`m OmVm h¡Ÿ&
looks as shown below: BgH$m n[anW Bg Vah hmoJm…
Carry
A C 1
H.A. C 2
B
H.A.
C
C Sum =
We can replace each Half Adder with one àË`oH$ hm\$ ES>a Ho$ ñWmZ na EH$ AND JoQ> VWm
AND gate and one XOR gate to provide the EH$ XOR JoQ> aIZo na {ZåZ Vm{H©$H$ n[anW àmá hmoVm
following logic circuit of a Full Adder: h¡ Bg_| g^r Xmo BZnwQ>m| dmbo JoQ> h¢…