Page 21 - ASME INTERPACK 2018 Program

Workshops
7-5 - HEAT SINK ADDITIVE MANUFACTURING WORKSHOP
WEDNESDAY, AUGUST 29, 2018
4:45 PM – 6:15 PM
ROOM: JACKSON, SECOND FLOOR
WORKSHOP TEAM: Joshua Gess, Oregon State University; Amy
Marconnet, Purdue University; Ronald Warzoha, United States Naval
Academy; Ankur Jain, University of Texas-Arlington; Naveenan
Thiagarajan, GE Global Research; Rick Eiland, Dell; Lauren Boteler,
Army Research Laboratory; Damena Agonafer, Washington University in
St. Louis; Travis Mayberry, Raytheon
Abstract: The ASME K-16 Student Design Competition Committee is
comprised of individuals dedicated to engaging, inspiring, and
empowering this field’s next generation of technical leaders. The
committee members come from diverse backgrounds including industry,
academia, and government laboratories. This team is passionate about
networking with young and energetic students who are actively trying to everywhere, and increasing interest in artificial intelligence (AI) & Virtual
build a pathway to lifelong careers and contributions in this technical Reality (VR) , the pace of innovation is increasing to meet these
community. challenges. What are the paths forward?
7-7 - HETEROGENEOUS INTEGRATION ROADMAP WORKSHOP (HIR)
THURSDAY, AUGUST 30, 2018
3:15 PM – 6:15 PM
ROOM: MASON I & II, SECOND FLOOR
Ravi Mahajan,
Intel Corporation, Santa Clara, CA
Abhijit Dasgupta,
University of Maryland, College Park, MD
Rockwell Hsu,
Cisco Systems
William Bottoms
General Partner of Patricof & Co. Ventures
Mark Shaw,
Director of Hardware Engineering, Microsoft
Meyya Meyyappan,
NASA Ames Research Center
Abstract: Our Industry has reinvented itself through multiple disruptive
changes in technologies, products and markets. With the rapid migration
of logic, memory and applications to the Cloud infrastructures, Data
Centers and 5G Networks, the Internet of Things (IoT) to internet of
everything (IOE), Autonomous Vehicles, the proliferation of Smart Devices
The IEEE Heterogeneous Integration Technology Roadmap (HIR), is
sponsored by the IEEE Electronic Packaging Society (EPS), the Electron
Devices Society (EDS), Photonics Society together with ASME EPPD and
SEMI. It will address the future directions of heterogeneous integration
technologies and applications serving future markets and applications, so
very crucial to our profession, our industries, academic and research
communities. Following the spirit of ITRS, the HIR is a pre-competitive
technology roadmap provides long-term vision to identify the needs of
future technology challenges, roadblocks, and potential solutions focused
on system integration and broad market applications in order to accelerate
progress for the broad electronics industry.
Biography: Ravi Mahajan is an Intel Fellow and the Co-director of
Pathfinding and Assembly and Packaging technologies for 7nm silicon and
beyond in the Technology and Manufacturing Group at Intel Corporation.
He has led efforts to define and set strategic direction for package
architecture, technologies and assembly processes at Intel since 2000,
spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi holds 21
more than 40 patents (including the original patent for a silicon bridge that
became the foundation for Intel’s Embedded Multi-Die Interconnect
Bridge technology) and has written several book chapters and more than
30 papers on topics related to his area of expertise. He has been
nominated as an IEEE CPMT Distinguished Lecturer. He is one of the
founding editors for the Intel Assembly and Test Technology Journal
(IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the
IEEE Transactions of the CPMT. Additionally he has been long associated
with ASME’s InterPACK conference and was Conference Co-Chair of the
2017 Conference. Ravi is a Fellow of two leading societies, ASME and
IEEE.
Biography: Abhijit Dasgupta is Jeong H. Kim Professor of Mechanical
Engineering at the University of Maryland (UMD), with research
experience in the microscale and nanoscale mechanics and reliability
physics of engineered materials used in conventional and additively
manufactured 3D flexible electronic packaging and intelligent
microsystems. He holds a Ph.D. in Theoretical and Applied Mechanics
from the University of Illinois at Urbana-Champaign (UIUC), and has been a