Page 77 - GIGABYTE Service Manual-v3.0-110101

GTLREF fail would also cause unable to detect CPU.

Figure 5-4: FF/00 Cause by Voltage-2

5.1.4 FF/00 cause by Others

Example: Intel

965P-DS3 1.0 identified by:
01. Post code FF.
02. –HINIT impedance open.
03. SB open and swap ok.
Signal Explanation:

INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor then
begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands
of all processor FSB agents. If INIT# is sampled active on the active to inactive
transition of RESET#, then the processor executes its Built-in Self-Test (BIST).
Repairing Notes:

The signal also needs to check:
A20M#, DPRSTP#. DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
SMI#3, STPCLK#, PWRGOOD, SLP#, BSEL [2:0]

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