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• Parallel ALUs

• Parallel processors Figure 17.16 illustrates the first two of these approaches. We have already
discussed pipelining in Chapter 12. Here the concept is extended to the operation of the ALU. Because
floating-point operations are rather complex, there is opportunity for decomposing a floating-point
operation into stages, so that different stages can operate on different sets of data concurrently.
This is illustrated in Figure 17.17a. Floating-point addition is broken up into four stages (see Figure 9.22):
compare, shift, add, and normalize. A vector of numbers is presented sequentially to the first stage.

As the processing proceeds, four different sets of numbers will be operated on concurrently in the
pipeline. It should be clear that this organization is suitable for vector processing.

To see this, consider the instruction pipelining described in Chapter 12. The processor goes through a
repetitive cycle of fetching and processing instructions. In the absence of branches, the processor is
continuously fetching instructions from sequential locations. Consequently, the pipeline is kept full and
a savings in time is achieved. Similarly, a pipelined ALU will save time only if it is fed a stream of data
from sequential

Figure 17.16 Approaches to Vector Computatio

locations. A single, isolated floating-point operation is not speeded up by a pipeline. The speedup is
achieved when a vector of operands is presented to the ALU. The control unit cycles the data through

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